A bandwidth-efficient architecture for media processing

被引：63

作者：

Rixner, S ^{[1
]}

Dally, WJ ^{[1
]}

Kapasi, UJ ^{[1
]}

Khailany, B ^{[1
]}

López-Lagunas, A ^{[1
]}

Mattson, PR ^{[1
]}

Owens, JD ^{[1
]}

机构：

[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA

来源：

31ST ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/MICRO.1998.742118

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are poorly matched to conventional microprocessor architectures, they are a good fit for modern VLSI technology with its high arithmetic capacity but limited global bandwidth. The stream programming model, in which an application is coded as streams of data records passing through computation kernels, exposes both parallelism and locality in media applications that can be exploited by VLSI architectures. The Imagine architecture supports the stream programming model by providing a bandwidth hierarchy tailored to the demands of media applications. Compared to a conventional scalar processor; Imagine reduces the global register and memory bandwidth required by typical applications by factors of 13 and 21 respectively This bandwidth efficiency enables a single chip Imagine processor to achieve a peak performance of 16.2GFLOPS (single-precision floating point) and sustained performance of up to 8.5GFLOPS an media processing kernels.

引用

页码：3 / 13

页数：11