Reliable threshold voltage determination for sub-0.1μm gate length MOSFET's

被引：8

作者：

Tsuno, M ^{[1
]}

Suga, M ^{[1
]}

Tanaka, M ^{[1
]}

Shibahara, K ^{[1
]}

Miura-Mattausch, M ^{[1
]}

Hirose, M ^{[1
]}

机构：

[1] Hiroshima Univ, Res Ctr Nanodevices & Syst, Higashihiroshima, Japan

来源：

PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 | 1998年

关键词：

D O I：

10.1109/ASPDAC.1998.669419

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A reliable method to determine the threshold voltage V-th for MOSFETs with gate length down to sub-0.1 mu m has been developed. The method determines V-th by Linear extrapolation of the transconductance g(m) to zero and is therefore named "GMLE method". 2D simulations were performed to extract the physical meaning of the method and to prove its reliability for different technologies. The results reveal that determined V-th values always meet the threshold condition i.e. the onset of inversion layer build-up.

引用

页码：111 / 116

页数：6