Kerneltron: Support vector "machine" in silicon

被引:96
作者
Genov, R [1 ]
Cauwenberghs, G [1 ]
机构
[1] Johns Hopkins Univ, Dept Elect & Comp Engn, Baltimore, MD 21218 USA
来源
IEEE TRANSACTIONS ON NEURAL NETWORKS | 2003年 / 14卷 / 05期
基金
美国国家科学基金会;
关键词
analog array processors; analog-to-digital conversion (ADC); charge-injection device (CID); dynamic random-access memory (DRAM); matrix-vector multiplication (MVM); oversampling quantization; pattern recognition; support vector machines (SVMs); vector quantization (VQ);
D O I
10.1109/TNN.2003.816345
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Detection of complex objects in streaming video poses two fundamental challenges: training from sparse data with proper generalization across variations in the object class and the environment; and the computational power required of the trained classifier running real-time. The Kerneltron supports the generalization performance of a support vector machine (SVM) and offers the bandwidth and efficiency of a massively parallel architecture. The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions. At the core of the Kerneltron is an internally analog, fine-grain computational array. performing externally digital inner-products between an incoming vector and each of the stored support vectors. The three-transistor unit cell in the array combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Precise digital outputs are obtained through oversampled quantization of the analog array outputs combined with bit-serial unary encoding of the digital inputs. The 256 input, 128 vector Kerneltron measures 3 min x 3 mm in 0.5 mum CMOS, delivers 6.5 GMACS throughput at 5.9 mW power, and attains 8-bit output resolution.
引用
收藏
页码:1426 / 1434
页数:9
相关论文
共 28 条
[1]  
ANGUITA D, 1998, ELECT LETT, V34
[2]  
Boser B. E., 1992, Proceedings of the Fifth Annual ACM Workshop on Computational Learning Theory, P144, DOI 10.1145/130385.130401
[3]   A tutorial on Support Vector Machines for pattern recognition [J].
Burges, CJC .
DATA MINING AND KNOWLEDGE DISCOVERY, 1998, 2 (02) :121-167
[4]  
CAUWENBERGHS G, 1999, LEARNING SILICON ANA
[5]  
CAUWENBERGHS G, 2001, P IEEE ADV NEUR INF
[6]   A CCD PROGRAMMABLE SIGNAL PROCESSOR [J].
CHIANG, AM .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (06) :1510-1517
[7]   Silicon support vector machine with on-line learning [J].
Genov, R ;
Chakrabartty, S ;
Cauwenberghs, G .
INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE, 2003, 17 (03) :385-404
[8]   Charge-mode parallel architecture for vector-matrix multiplication [J].
Genov, R ;
Cauwenberghs, G .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2001, 48 (10) :930-936
[9]  
GENOV R, 2002, P IEEE ADV NEUR INF
[10]  
GENOV R, 2002, THESIS J HOPKINS U B