Materials and processing for 0.25 mu m multilevel interconnect

A new generation of interconnect schemes is required for high performance ULSI. This involves developing process modules aimed at reducing RC delay and power consumption, as well as developing new equipment technology to support these processes. In the materials area, the most significant challenge is to define a workable and reliable combination of high conductivity metals (Al(Cu), Cu) with a low dielectric constant insulator (starting with fluorinated silicon oxide). As far as processing is concerned, the key technological issues that we will address in this paper are (i) etching dielectrics and metals with high aspect ratio (4:1 for contact/via and greater than 1.5:1 for lines/trenches) and (ii) filling these aggressive topologies using dielectric films with high gap-filling capabilities and conformal/planarizing CVD and PVD metal deposition. Besides the option of using SiOF dielectric and oxide CMP, four process modules of interconnects can be highlighted: (1) gap-fill oxide/W interconnect and/or via plug/metal etch; (2) gap-fill oxide/via fill and planarized Al/metal etch; (3) metal plug/metal damascene; and (4) Cu dual damascene. Since time-to-market will still be very critical for fabrication at 0.25 mu m technology, typically for 200 mm and 300 mm wafers, the challenge is clearly to achieve successful vertical and horizontal integration of these modules. As a result, more than ever, suppliers and chip manufacturers have to work very closely at early stages of technology development. Examples of joint development programs leading to new breakthroughs in technology and reactor design will be discussed.