Via-filling using electroplating for build-up PCBs

被引:103
作者
Kobayashi, T [1 ]
Kawasaki, J [1 ]
Mihara, K [1 ]
Honma, H [1 ]
机构
[1] Kanto Gakuin Univ, Fac Engn, Kanazawa Ku, Yokohama, Kanagawa 2360032, Japan
关键词
electroplating; micro-via; filling; build-up PCB;
D O I
10.1016/S0013-4686(01)00592-8
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
The requirement of miniaturization of printed circuit boards has been increased with downsizing of electronic devices. However, the conventional multi-layered printed circuit boards are now facing the limitation for high mounting densities. Therefore, a newly developed build-up process has emerged as a new multi-layered printed circuit board manufacturing process. This new technology has adopted the micro-vias for connection between each conductive layer. If the micro-vias can be filled with copper metal, signal propagation is enhanced by via-on-via connection. Therefore, effective circuitry can be achieved. However, filling the conductive layer with the micro-vias is becoming difficult using the conventional plating process or the electrical conductive paste. Filling of the micro-vias by electroplating is studied, It was confirmed that copper sulfate concentration in copper sulfate plating bath is one of the key factors to fill the micro-vias, and the vias can be filled using a high copper concentration bath. (C) 2001 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:85 / 89
页数:5
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