A 90 nm low power 32K-byte embedded SRAM with gate leakage suppression circuit for mobile applications

被引：17

作者：

Nii, K ^{[1
]}

Tenoh, Y ^{[1
]}

Yoshizawa, T ^{[1
]}

Imaoka, S ^{[1
]}

Tsukamoto, Y ^{[1
]}

Yamagami, Y ^{[1
]}

Suzuki, T ^{[1
]}

Shibayama, A ^{[1
]}

Makino, H ^{[1
]}

Iwade, S ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, Syst LSI Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

10.1109/VLSIC.2003.1221217

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In sub100 nm generation, gate tunneling leak current increases and dominates total standby leak current of LSI based on decreasing gate oxide thickness. We propose reducing gate leak current in SRAM using Local DC Level Control (LDLC) and an. Automatic Gate Leakage Suppression Driver to reduce gate leak current in the peripheral circuit. We designed and fabricated a 32KB 1-port SRAM using 90 nm CMOS technology. The 6T-SRAM-cell size is 1.25 um(2). Evaluation showed that the standby current of 32KB SRAM is 1.2 uA at 1.2 V and room temperature. It is reduced to 7.5 % of conventional SRAM.

引用

页码：247 / 250

页数：4