On-chip integration of dipole antenna and VCO using standard BiCMOS technology for 10 GHz applications

被引：19

作者：

Touati, F ^{[1
]}

Pons, M ^{[1
]}

机构：

[1] France Telecom, R&D, F-38243 Meylan, France

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257180

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The study of on-chip integration of a 10 GHz dipole antenna with a VCO using standard BiCMOS7(TM) (0.25 mum) STm technology has been carried out. The antenna configuration, which has been chosen, is a folded dipole, which allows reducing the chip dimensions to 2.7 x 4.48 mm(2). The first measurement results are in rather good agreement with the simulated results. For a RF power injected from VCO to the antenna of -7dBm (0.2mW), the EIRP of antenna is about -15dBm. Thus the estimated value of antenna isotropic gain is about -8 dBi. This result is consistent with simulation values of radiation efficiency of the order of 10%.

引用

页码：493 / 496

页数：4