Parametric yield optimization of MOS IC's affected by device mismatch

被引：1

作者：

Conti, M ^{[1
]}

Crippa, P ^{[1
]}

Orcioni, S ^{[1
]}

Turchetti, C ^{[1
]}

机构：

[1] Univ Ancona, Dipartimento Elettron & Automat, I-60131 Ancona, Italy

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2001年 / 29卷 / 03期

关键词：

parametric yield; device mismatch; optimization; statistical variations;

D O I：

10.1023/A:1011213414261

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method.

引用

页码：181 / 199

页数：19

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