Logic gates and memory cells based on single C60 electromechanical transistors

The equivalent electrical circuit of a single C-60 electromechanical transistor in a planar lay-out is presented using its experimental STM characteristics. This circuit is used to demonstrate that such a hybrid molecular electronic device can be used as a class A amplifier, a NOT or NOR gate and to implement an SRAM memory point. All the devices are simulated using the SPICE routine to find their optimum load resistance and cantilever grid size. The class A amplifier can operate with a cut-off frequency of a few gigahertz while the logic gate and memory are limited to a few tens of megahertz, but for a very small power design in the picowatt range.