Performance and variability optimization strategies in a Sub-200mV, 3.5pJ/inst, 11 nW subthreshold processor

被引：46

作者：

Hanson, Scott ^{[1
]}

Zhai, Bo ^{[1
]}

Seok, Mingoo ^{[1
]}

Cline, Brian ^{[1
]}

Zhou, Kevin ^{[1
]}

Singhal, Meghna ^{[1
]}

Minuth, Michael ^{[1
]}

Olson, Javin ^{[1
]}

Nazhandali, Leyla ^{[1
]}

Austin, Todd ^{[1
]}

机构：

[1] Univ Michigan, Ann Arbor, MI 48109 USA

来源：

2007 Symposium on VLSI Circuits, Digest of Technical Papers | 2007年

关键词：

subthreshold; variability; body-bias; low power;

D O I：

10.1109/VLSIC.2007.4342694

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A robust, energy efficient subthreshold (sub-V-th) processor has been designed and tested in a 0.13 mu m technology. The processor consumes 11nW at V-dd = 160mV and 3.5pJ/inst at V-dd = 350mV. Variability and performance optimization techniques are investigated for sub-V-th circuits.

引用

页码：152 / 153

页数：2