Novel lithography-independent pore phase change memory

被引：101

作者：

Breitwisch, M. ^{[1
]}

Nirschl, T. ^{[2
]}

Chen, C. F. ^{[4
]}

Zhu, Y. ^{[1
]}

Lee, M. H.

Lamorey, M. ^{[5
]}

Burr, G. W. ^{[7
]}

Joseph, E. ^{[1
]}

Schrott, A. ^{[1
]}

Philipp, J. B. ^{[3
]}

Cheek, R. ^{[1
]}

Happ, T. D. ^{[3
]}

Chen, S. H. ^{[4
]}

Zaidi, S. ^{[3
]}

Flaitz, P. ^{[6
]}

Bruley, J. ^{[6
]}

Dasaka, R. ^{[1
]}

Rajendran, B. ^{[1
]}

Rossnagel, S. ^{[1
]}

Yang, M. ^{[1
]}

Chen, Y. C. ^{[4
]}

Bergmann, R. ^{[3
]}

Lung, H. L. ^{[4
]}

Lam, C. ^{[1
]}

机构：

[1] IBM TJ Watson Res Ctr, 1101 Kitchawan Rd, Yorktown Hts, NY 10598 USA

[2] Infineon Technol, Neubiberg, Germany

[3] Qimonda, Munich, Germany

[4] Macronix, Hsinchu, Taiwan

[5] IBM Essex Junction, Essex Jct, VT USA

[6] IBM Fishkill, Fishkill, NY USA

[7] IBM Almaden Res Ctr, San Jose, CA USA

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339743

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformal deposition. Fully integrated 256kbit test chips have been fabricated in 180nm CMOS technology. We report SET times of 80ns, RESET currents less than 250 mu A, and accurate sub-lithographic CDs that can be less than 20% the size of the lithographically-defined diameter.

引用

页码：100 / +

页数：2