Embedded trench DRAMs for sub-0.10-μm generation by using hemispherical-grain technique and LOCOS collar process

被引：4

作者：

Saida, S ^{[1
]}

Sato, T

Sato, M

Kito, M

机构：

[1] Toshiba Co Ltd, Adv ULSI Proc Engn Dept 4, Isogu Ku, Kanagawa 2358522, Japan

[2] Toshiba Microelect Corp, ULSI Proc & Environm Engn Grp, Isogo Ku, Kanagawa 2358522, Japan

[3] Toshiba Co Ltd, Adv Memory Prod Dev Dept, Yokkaichi, Mie, Japan

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 2001年 / 14卷 / 03期

关键词：

cost of ownership (COO); hemispherical grain (HSG); LOCOS collar; raw process time (RPT); trench DRAM;

D O I：

10.1109/66.939812

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

For the future System on Chip era, the embedded DRAM is one of the most important devices. Since the kind of the devices increase and each device must be produced of only 10 000 wafers, it is difficult to withdraw the investment cost to fabricate each device. To suppress the investment cost, the devices must be shrunk by changing the integration and the materials as less as possible. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy achieves 30 fF/cell for the 0.08-mum trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08-mum trench to 80% of 0.18-mum trench, with an investment of only $1.6 M. It is achieved by the LOCOS collar process and HSG technique.

引用

页码：196 / 201

页数：6