Nonideal battery and main memory effects on CPU speed-setting for low power

被引：29

作者：

Martin, TL ^{[1
]}

Siewiorek, DP

机构：

[1] Univ Alabama, Dept Elect & Comp Engn, Huntsville, AL 35899 USA

[2] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2001年 / 9卷 / 01期

基金：

美国国家科学基金会;

关键词：

battery modeling; low power design; low power dissipation; system level; tradeoffs; variable voltage;

D O I：

10.1109/92.920816

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper explores the system-level power-performance tradeoffs of dynamically varying CPU speed. Previous work in CPU speed-setting considered only the power of the CPU and only CPUs that vary supply voltage with frequency. This work takes a broader approach, considering total system power, battery capacity, and main memory bandwidth, The results, which are up to a factor of four less than ideal, show that ah three must be considered when setting the CPU speed.

引用

页码：29 / 34

页数：6

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