Impact of Mobility Boosters (XsSOI, CESL, UN gate) on the Performance of ⟨100⟩ or ⟨110⟩ oriented FDSOI cMOSFFTs for the 32nm Node

被引：35

作者：

Andrieu, F. ^{[1
]}

Faynot, O. ^{[1
]}

Rochette, F. ^{[1
]}

Barbe, J.-C. ^{[1
]}

Buj, C. ^{[1
]}

Bogumilowicz, Y. ^{[1
]}

Allain, F. ^{[1
]}

Delaye, V. ^{[1
]}

Lafond, D. ^{[1
]}

Aussenac, F. ^{[1
]}

Feruglio, S. ^{[1
]}

Eymery, J. ^{[1
]}

Akatsu, T. ^{[1
]}

Maury, P. ^{[1
]}

Brevard, L. ^{[1
]}

Tosti, L. ^{[1
]}

Dansas, H. ^{[1
]}

Rouchouze, E. ^{[1
]}

Hartmann, J. -M. ^{[1
]}

Vandroux, L. ^{[1
]}

Casse, M. ^{[1
]}

Boeuf, F. ^{[1
]}

Fenouillet-Beranger, C. ^{[1
]}

Brunier, F. ^{[1
]}

Cayrefourcq, I. ^{[1
]}

Mazure, C. ^{[1
]}

Ghibaudo, G. ^{[1
]}

Deleonibus, S. ^{[1
]}

机构：

[1] CEA LETI MINATEC, F-38054 Grenoble, France

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339723

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we integrated 1.9GPa eXtra-strained Silicon On Insulator (XsSOI) substrates in FDSOI n and pMOSFETs with gate length (L-G) and width (W) down to 25nm. Due to the high stress levels, significant I-ON-I-OFF improvements were obtained not only for nMOS but also for pMOS. We compared those results with the performance of devices strained by Contact Etch Stop Layer (CESL), for different device orientations (< 110 > or < 100 >) and feature sizes (LO, W). We demonstrate that, similarly to XsSOL a single tensile CESL can improve both n and pMOS performance, leading to I-ON,I-n 700 mu A/mu m and ION,P 430 mu A/mu m at I-OFF=140 mu A/mu m, this for L-G < 35nm, W=50nm and V-DD=1 V along the < 100 > direction.

引用

页码：50 / 51

页数：2

共 10 条

[1]

AKATSU T, 2006, ECS, V12, P107

[2]

ANDRIEU F, 2006, IEDM, P641

[3]

Andrieu F., 2006, VLSI S, P134

[4]

ANG KW, 2006, VLSI TECH, P66

[5] PIEZORESISTIVITY EFFECTS IN MOS-FET USEFUL FOR PRESSURE TRANSDUCERS [J].

CANALI, C ;

FERLA, G ;

MORTEN, B ;

TARONI, A .

JOURNAL OF PHYSICS D-APPLIED PHYSICS, 1979, 12 (11) :1973-1983

[6]

Krivokapic Z., 2003, Int. Electron Devices Meeting Tech. Dig, P445

[7]

Rim K, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P49

[8]

Saito S., 2006, VLSI TECH, P150

[9]

XIONG W, 2006, EDL, V27, P612

[10] Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics [J].

Yang, M ;

Gusev, EP ;

Ieong, MK ;

Gluschenkov, O ;

Boyd, DC ;

Chan, KK ;

Kozlowski, PM ;

D'Emic, CP ;

Sicina, RM ;

Jamison, PC ;

Chou, AI .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (05) :339-341

← 1 →