An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists

被引：122

作者：

Elbirt, AJ ^{[1
]}

Yip, W ^{[1
]}

Chetwynd, B ^{[1
]}

Paar, C ^{[1
]}

机构：

[1] Worcester Polytech Inst, Dept Elect & Comp Engn, Worcester, MA 01609 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2001年 / 9卷 / 04期

基金：

美国国家科学基金会;

关键词：

algorithm agility; block cipher; cryptography; field-programmable gate array (FPGA); VHDL;

D O I：

10.1109/92.931230

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The technical analysis used in determining which of the potential Advanced Encryption Standard candidates was selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as field-programmable gate arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms, as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high-throughput implementations, which are required to support security for current and future high bandwidth applications. Finally, the implementations of each algorithm will be compared in an effort to determine the most suitable candidate for hardware implementation within commercially available FPGAs.

引用

页码：545 / 557

页数：13

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