Heap charge pump optimisation by a tapered architecture

被引：9

作者：

Arona, R ^{[1
]}

Bonizzoni, E ^{[1
]}

Maloberti, F ^{[1
]}

Torelli, G ^{[1
]}

机构：

[1] Univ Pavia, Dept Elect, I-27100 Pavia, Italy

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1464984

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The heap charge pump represents an attractive voltage multiplier scheme in integrated circuits where only low-voltage devices are available. This paper presents a performance optimisation of the heap charge pump achieved by using a tapered architecture. The proposed optimisation allows improvements on the order of 30% in terms of maximum output voltage as compared to the conventional heap charge pump. A mathematical description of both the conventional and the proposed structure was developed. MATLAB (R)-based simulation results demonstrate the effectiveness of the proposed scheme.

引用

页码：1903 / 1906

页数：4