Design of a low output voltage DC/DC converter for Telecom application with a new scheme for self-driven synchronous rectification

被引：16

作者：

Alou, P ^{[1
]}

Cobos, JA ^{[1
]}

Uceda, J ^{[1
]}

Rascón, M ^{[1
]}

de la Cruz, E ^{[1
]}

机构：

[1] Univ Politecn Madrid, DIE, E-28006 Madrid, Spain

来源：

APEC'99: FOURTEENTH ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, CONFERENCE PROCEEDINGS, VOLS 1 & 2 | 1999年

关键词：

D O I：

10.1109/APEC.1999.750470

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the design and experimental results of a very low output voltage DC/DC converter for a specific Telecom. application (1.5V, 10A) is presented and analyzed. Several topologies have been compared and analyzed, not only from the point of view of size (15W/inch(3), 10mm of height) and efficiency (> 85%), but also regarding the dynamic response of the converter to supply pulsating loads (80A/mu s). A new driving scheme for Self Driven Synchronous Rectification (SDSR) is used. It allows to use the standard Half Bridge topology, which, is very suitable for such a wide input voltage range (36V - 72V).

引用

页码：866 / 872

页数：3