A 700+-mW class D design with direct battery hookup in a 90-nm process

被引：43

作者：

Forejt, B ^{[1
]}

Rentala, V ^{[1
]}

Arteaga, JD ^{[1
]}

Burra, G ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75243 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 09期

关键词：

class D amplifier; common mode rejection ratio (CMRR); efficiency; electromagnetic interference (EMI); low drop-out regulator (LDO); power supply rejection ratio (PSRR); pulse-width modulation (PWM); signal-to-noise ratio (SNR); system-on-chip (SOC); total harmonic distortion (THD); ultradeep submicron (UDSM);

D O I：

10.1109/JSSC.2005.848147

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A "battery connect" compatible class D (switching) amplifier which is fully integrated in a 90-nm digital CMOS process is presented. The integration of the amplifier requires no additional masks, processing, or cost. This paper includes a brief description of the circuit techniques that enable direct battery (2.7-5.4 V) connection and allow support > 6.7 V-P2P (700 mW into 8 Omega) output swing from a 4.2-V supply using devices that operate solely with low gate voltages. The achieved SNR over an audio (20 Hz to 20 kHz) bandwidth > 98.5 dB and the total harmonic distortion (THD) is better than 0.03% at 500 mW. Efficiency is greater than 75% above 375 mW. The power supply rejection ratio, which is a crucial parameter in modules connected directly to the battery, is measured at 70 dB at 217 Hz. The area of the switching amplifier is < 0.44 mm(2), where the power devices occupy approximately 20% of the total.

引用

页码：1880 / 1887

页数：8

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