Four-quadrant one-transistor-synapse for high-density CNN implementations

被引：14

作者：

Dominguez-Castro, R ^{[1
]}

Rodriguez-Vazquez, A ^{[1
]}

Espejo, S ^{[1
]}

Carmona, R ^{[1
]}

机构：

[1] Univ Sevilla, CSIC, Ctr Nacl Microelect, Inst Microelect Sevilla, Seville 41012, Spain

来源：

CNNA 98 - 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/CNNA.1998.685377

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a linear; four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology: It is specially suited for translationally-invariant processing arrays with local connectivity and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.

引用

页码：243 / 248

页数：4