A 5-GHz BiCMOS RFIC front-end for IEEE 802.11 a/HiperLAN wireless LAN

An RFIC for the IEEE 802.11a/HiperLAN WLAN standard has been designed and fabricated in a 0.5-mum SiGe BiCMOS technology. The IC, which is part of a superheterodyne radio, comprises an RF synthesizer and up/down converters from the 5.18-5.8-GHz UNII band to an 880-MHz IF. In high gain, the receiver exhibits a 5.7-dB noise figure and an input referred third-order intercept (IIP3) of -11 dBm with 31 dB of conversion gain. The receiver has a 20-dB gain step resulting in a low gain state of 11 dB with an 18-dB noise figure and an IIP3 of +6 dBm. The transmitter operating at 2.7 V has an output referred third-order intercept of +23 dBm and an output -1-dB compression of +13 dBm with 20 dB of conversion gain. An integrated 0.5-mum pMOS VCO exhibits a phase noise of -119 dBc/Hz at 1-MHz offset. An integer-N synthesizer with trimodulus prescaler has an integrated phase noise from 2 kHz to 1 MHz of -33 dBc. An air link was established between two RFICs and orthogonal frequency division multiplexing (OFDM) modulation was transmitted and received operating in 64 QAM mode at 54 Mb/s. With the link established, the measured received error vector magnitude was -28 dB, meeting the 802.11a standard.