Dry etch sequencing induced gate oxide degradation due to metallic contamination in 0.25 μm CMOS manufacturing

被引:2
作者
Hughes, J [1 ]
Perera, A [1 ]
Hernandez, I [1 ]
Parihar, P [1 ]
Karupanna, K [1 ]
Vasek, J [1 ]
Hanna, J [1 ]
Nagy, A [1 ]
Lii, T [1 ]
Reese, M [1 ]
Rose, J [1 ]
Arnold, J [1 ]
Cain, J [1 ]
Mattay, S [1 ]
Porter, J [1 ]
Razumovsky, O [1 ]
Chesnut, T [1 ]
Kaiser, A [1 ]
Poon, S [1 ]
机构
[1] Motorola Inc, MOS 13, Austin, TX 78721 USA
来源
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年
关键词
D O I
10.1109/IEDM.1998.746368
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To ensure maximum tool utilization in high volume semiconductor manufacturing, multiple etch recipes may be implemented on a given etch chamber configuration. Due to the increased process complexity required for 0.25 mu m semiconductor fabrication, residual effects in chambers and interaction between etch recipes can change individual etch process outputs. Described below is 40 Angstrom gate oxide degradation due to residual metallic contamination in an etch chamber caused by a previous contact etch process, in high volume 0.25 mu m CMOS manufacturing. Chamber seasoning, the specific combination of etch processes run due to product needs, post-etch cleans, and gate polysilicon doping all have a significant effect on the degree of oxide degradation caused. Also discussed is the impact of the degraded oxide on circuit yield and reliability.
引用
收藏
页码:337 / 340
页数:4
相关论文
共 3 条
[1]  
KERN W, 1970, RCA REV, V31, P187
[2]  
SUN WT, 1997, L APPL PHYS, V36, pL89
[3]  
TSUI P, 1998, VLSI TECH, P152