Design considerations for VRM transient response based on the output impedance

被引：126

作者：

Yao, KW ^{[1
]}

Xu, M ^{[1
]}

Meng, Y ^{[1
]}

Lee, FC ^{[1
]}

机构：

[1] Virginia Polytech Inst & State Univ, Ctr Power Elect Syst, Bradley Dept Elect & Comp Engn, Blacksburg, VA 24061 USA

来源：

IEEE TRANSACTIONS ON POWER ELECTRONICS | 2003年 / 18卷 / 06期

基金：

美国国家科学基金会;

关键词：

output impedance; transient analysis; voltage regulator;

D O I：

10.1109/TPEL.2003.818824

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the transient response of voltage regulator modules (VRMs) based on the small-signal models. The concept of constant resistive output impedance design for the VRM is proposed, and its limitations in applications are analyzed. The impacts of the output filter and the feedback control bandwidth show that there is an optimal design that allows the VRM to achieve fast transient response, small size and good efficiency. Simulations and experimental results prove the theoretical analysis.

引用

页码：1270 / 1277

页数：8

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