Throughput enhancement strategy of maskless electron beam direct writing for logic device

被引：37

作者：

Inanami, R ^{[1
]}

Magoshi, S ^{[1
]}

Kousai, S ^{[1
]}

Hamada, M ^{[1
]}

Takayanagi, T ^{[1
]}

Sugihara, K ^{[1
]}

Okumura, K ^{[1
]}

Kuroda, T ^{[1
]}

机构：

[1] Toshiba Corp, Semicond Co, Proc & Mfg Engn Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904446

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

引用

页码：833 / 836

页数：4

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