A 200-MSPS 6-bit flash ADC in 0.6-μm CMOS

被引：15

作者：

Dalton, D ^{[1
]}

Spalding, GJ ^{[1
]}

Reyhani, H ^{[1
]}

Murphy, T ^{[1
]}

Deevy, K ^{[1
]}

Walsh, M ^{[1
]}

Griffin, P ^{[1
]}

机构：

[1] Analog Devices Inc, Design Dept, Limerick, Ireland

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1998年 / 45卷 / 11期

关键词：

analog; digital conversion; analog integrated circuits; comparators; read channel;

D O I：

10.1109/82.735355

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 6-bit Flash analog-to-digital converter (ADC) which performs the sampling function in a partial-response, maximum-likelihood (PRML) disk drive read channel. It operates with sampling frequencies up to 200 MSPS and achieves an effective number of bits (ENOB) of 5.5 bits with F-in = 50 MHz and 5.0 bits at F-in = 100 MHz. It consumes 380 mW at 5 V and occupies 2.7 mm(2), Other features include a bit-error rate of <1e-10 and a programmable nonlinear transfer function.

引用

页码：1433 / 1444

页数：12

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