Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

被引：39

作者：

Goto, K ^{[1
]}

Satoh, S ^{[1
]}

Ohta, H ^{[1
]}

Fukuta, S ^{[1
]}

Yamamoto, T ^{[1
]}

Mori, T ^{[1
]}

Tagawa, Y ^{[1
]}

Sakuma, T ^{[1
]}

Saiki, T ^{[1
]}

Shimamune, Y ^{[1
]}

Katakami, A ^{[1
]}

Hatada, A ^{[1
]}

Morioka, H ^{[1
]}

Hayami, Y ^{[1
]}

Inagaki, S ^{[1
]}

Kawamura, K ^{[1
]}

Kim, Y ^{[1
]}

Kokura, H ^{[1
]}

Tamura, N ^{[1
]}

Horiguchi, N ^{[1
]}

Kojima, M ^{[1
]}

Sugii, T ^{[1
]}

Hashimoto, K ^{[1
]}

机构：

[1] Fujitsu Ltd, Tokyo 1970833, Japan

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419111

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Strain Enhancing Laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (Stage IV) were demonstrated with a drive currents of 1120uA/um and 690uA/um at Vdd=1V/Ioff=100nA/um, respectively. This is the best drive current among the resent reports.

引用

页码：209 / 212

页数：4

共 7 条

[1]

Chan V, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P77

[2]

Chidambaram PR, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P48

[3]

Fung SKH, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P92

[4]

Giles MD, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P118

[5]

Goto K, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P623

[6]

Mistry K, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P50

[7]

Yang FL, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P8

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