The transmogrifier-2: A 1 million gate rapid-prototyping system

被引:13
作者
Lewis, DM [1 ]
Galloway, DR [1 ]
van Ierssel, M [1 ]
Rose, J [1 ]
Chow, P [1 ]
机构
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada
基金
加拿大自然科学与工程研究理事会;
关键词
architecture; field programmable gate array (FPGA); memory; rapid prototype; scalability;
D O I
10.1109/92.678867
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes the Transmogrifier-2 (TM-2), a second-generation multifield programmable gate array (FPGA) rapid-prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGA's, four I-Cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a nonuniform partial crossbar, that provides a constant delay between any two FPGA's in the system. The TM-2 architecture is modular and scalable, meaning that systems of various sizes can be constructed from copies of the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with edge resolution of 10 ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications.
引用
收藏
页码:188 / 198
页数:11
相关论文
共 11 条
[1]  
*ALT CORP, 1996, ALT FLEX LOG HDB
[2]  
Amerson R., 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.95TB8077), P32, DOI 10.1109/FPGA.1995.477406
[3]  
Arnold J., 1992, P 4 ANN ACM S PAR AL, DOI [10.1145/140901.141896, DOI 10.1145/140901.141896]
[4]  
BUTTS M, 1992, P IEEE INT C COMP DE, P138
[5]  
Chan P. K., 1993, Proceedings IEEE Workshop on FPGAs for Custom Computing Machines (Cat. No.93TH0535-5), P152, DOI 10.1109/FPGA.1993.279468
[6]  
GALLOWAY D, 1995, P IEEE S FPGA CUST C
[7]  
GALLOWAY D, 1994, P 2 CAN WORKSH FIELD
[8]  
KHALID M, P CAN WORKSH FIELD P, P94
[9]  
SLIMANEKADI M, 1994, P 2 ANN WORKSH FPGA
[10]  
TESSIER R, 1994, P 2 ANN WORKSH FPGA