New frequency-locked loop based on CMOS frequency-to-voltage converter: Design and implementation

In this paper, we describe the architecture of a new CMOS fully integrated frequency-locked loop (FILL). The proposed FLL contains a frequency-to-voltage converter (FVC), an operational amplifier (opamp) and a differential voltage-controlled oscillator (WO). The operation of the proposed circuit is based on frequency comparison of a reference and feedback signals. The architecture of the FVC is built upon capacitors charge redistribution principle, whereas the architecture of the VCO is based on differential delay cells in order to minimize the effect of the power supply and the substrate noise. Simulation carried out with Hspice using the CMOS 0.35-mum process shows that the FLL is very fast and operates over a wide frequency range. Two versions of the FLL are reported; the basic architecture could show a static offset due to the two employed FVCs. To alleviate this effect, a second version is proposed to completely eliminate the offset. The area of the proposed FLL, is very small, and the design could be easily integrated in the same die together with other analog, digital and mixed-signal blocks. A functional test of five samples of a first version of this FLL proved that the proposed FLL works as expected from simulation results. Examples of the application of the proposed FLL are a high-precision VCO and a frequency synthesizer with true-fractional multiplication and division that does not require binary frequency dividers.