Getting to the bottom of deep submicron

In this tutorial, we take a fresh look at the problems posed by deep submicron (DSM) geometries and re-open the investigation into how DSM effects are most likely going to affect future design methodologies. We describe a comprehensive approach to accurately characterizing the device and interconnect characteristics of present and future process generations This approach results in the generation of a representative strawman technology that is used in conjunction with analytical models, simulation tools and empirical design data to obtain a realistic picture of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including delay degradation due to noise, on high-performance ASIC designs. Having determined the role of interconnect in performance, we then reconsider the impact of future processes on ASIC design methodology.