Parallelized Architecture of Multiple Classifiers for Face Detection

被引:24
作者
Cho, Junguk [1 ]
Benson, Bridget [1 ]
Mirzaei, Shahnam [2 ]
Kastner, Ryan [1 ]
机构
[1] Univ Calif San Diego, Dept Comp & Sci & Engn, La Jolla, CA 92093 USA
[2] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA USA
来源
2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS | 2009年
关键词
face detection; FPGA; Haar classifier; image processing; parallel architecture; real-time processing;
D O I
10.1109/ASAP.2009.38
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the paralletized architecture of multiple classifiers can have 3.3x performance gain over the architecture of a single classifier and an 84x performance gain over an equivalent software solution.
引用
收藏
页码:75 / +
页数:2
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