Tunnel oxide and ETOX™ flash scaling limitation

被引：35

作者：

Lai, S ^{[1
]}

机构：

[1] Intel Corp, Santa Clara, CA 95052 USA

来源：

SEVENTH BIENNIAL IEEE INTERNATIONAL NONVOLATILE MEMORY TECHNOLOGY CONFERENCE, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/NVMT.1998.723204

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Intrinsic tunnel oxide thickness limit is around 6 nm due to direct tunneling. In practical devices, the limit is 8 nm due to stress induced leakage after program and erase cycles. Nitridation reduces electron trapping but does not decrease the lower thickness limit. Operating voltages also do not scale well in flash memories. Voltages required for operation range from 10-12V for channel hot electron stacked gate devices to up to 20V for Fowler Nordheim tunnel and erase devices. This places limit in transistor channel and isolation scaling. Looking ahead, cell scaling beyond 0.13 mu m will be difficult unless there is major breakthrough. Multi level cell storage technology provides a cost effective alternative to process scaling. Feasibility studies showed that up to 16 levels or 4 bit per cell is possible with stacked gate. Stacked gate flash memory cell using channel hot electron programming is best suited for high density multi level cell technology.

引用

页码：6 / 7

页数：2