Face detection system for SVGA source with hecto-scale frame rate on FPGA board

被引：4

作者：

Ding, Zheng ^{[1
]}

Zhao, Feng ^{[2
]}

Shu, Wei ^{[3
]}

Wu, Min-You ^{[1
]}

机构：

[1] Shanghai Jiao Tong Univ, Dept Comp Sci & Engn, Shanghai 200240, Peoples R China

[2] Digilent Elect Technol Co Ltd, Shanghai, Peoples R China

[3] Univ New Mexico, Dept Elect & Comp Engn, Albuquerque, NM 87131 USA

来源：

MICROPROCESSORS AND MICROSYSTEMS | 2012年 / 36卷 / 04期

关键词：

Face detection system; Field programmable gate array; Haar feature; ARCHITECTURE;

D O I：

10.1016/j.micpro.2012.01.002

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes techniques for face detection using Haar-like features as weak classifiers and gives the implementation details for an FPGA development board. We analyze and discuss the relation between the system computation cost and selection of the image scaling factor. Based on the empirical results of our previous work, we give a new method to select the stop threshold for the image reduction process, which reduces the total computation by half. We present and implement an improved integral image pipeline calculation design. We also provide a color image output mode to let our system enjoy more human-oriented design. Test results show that the system achieves real-time face detection speed (100fps) and a high face detection rate (87.2%) for an SVGA (600 x 800) video source. The low power consumption (3.5 W) is another advantage over previous work. (C) 2012 Elsevier B.V. All rights reserved.

引用

页码：315 / 323

页数：9

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