Low VtNi-FUSICMOS technology using a DyO cap layer with either single or dual ni-phases

被引:12
作者
Yu, H. Y. [1 ]
Chang, S. Z. [2 ]
Veloso, A. [1 ]
Lauwers, A. [1 ]
Adelmann, C. [1 ]
Onsia, B. [1 ]
Van Elshocht, S. [1 ]
Singanamalla, R. [1 ]
Demand, M. [1 ]
Vos, R. [1 ]
Kauerauf, T. [1 ]
Brus, S. [1 ]
Shi, X. [1 ]
Kubicek, S. [1 ]
Vrancken, C. [1 ]
Mitsuhashi, R. [3 ]
Lehnen, P. [5 ]
Kittl, J. [4 ]
Niwa, M. [3 ]
Yin, K. M. [2 ]
Hoffinann, T. [1 ]
Degendt, S. [1 ]
Jurczak, M. [1 ]
Absil, P. [1 ]
Biesemans, S. [1 ]
机构
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[2] TSMC, B-3001 Leuven, Belgium
[3] Matsushita, B-3001 Leuven, Belgium
[4] TI, B-3001 Leuven, Belgium
[5] IMEC, Aixtron, B-3001 Leuven, Belgium
来源
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年
关键词
D O I
10.1109/VLSIT.2007.4339710
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper reports a novel approach to implement low V, Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 angstrom) can lower the NiSi FUSI nFET V, by 300mV/500mV on HfSiON/SiON (resulting in a V-t,V-lin of 0.25V/0.18V respectively), w/o compromising the Tin, (< 1 angstrom variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150x lower J(g) wrt SION. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n- and pFETs.
引用
收藏
页码:18 / +
页数:2
相关论文
共 5 条
[1]  
HOFFMANN T, 2006, IEDM, P10
[2]  
JUNG HS, 2006, TECH DIG S VLSI TECH, P204
[3]   Magnetic force-based multiplexed immunoassay using superparamagnetic nanoparticles in microfluidic channel [J].
Kim, KS ;
Park, JK .
LAB ON A CHIP, 2005, 5 (06) :657-664
[4]  
LEE T, 2006, EDL, P640
[5]  
YU HY, 2006, TECH VLSI, P120