FRAM cell design with high immunity to fatigue and imprint for 0.5μm 3V 1T1C 1M bit FRAM

被引：11

作者：

Tanaka, S ^{[1
]}

Ogiwara, R ^{[1
]}

Itoh, Y ^{[1
]}

Miyakawa, T ^{[1
]}

Takeuchi, Y ^{[1
]}

Doumae, S ^{[1
]}

Takenaka, H ^{[1
]}

Kamata, H ^{[1
]}

机构：

[1] Toshiba Corp, ULSI Device Engn Lab, Sakae Ku, Yokohama, Kanagawa 2478585, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746374

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new FRAM cell design with high immunity to fatigue and imprint has been proposed to achieve a megabit class FRAM with 1T1C cell structure, which has been applied to a IM bit FRAM operated fi om a 3V supply with 1T1C cell structure, 0.5 mu m rule and 3 mu m(2) capacitor area. The simulation result and imprint data predict a lifetime improved 7 orders longer than the conventional scheme.

引用

页码：359 / 362

页数：4