A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO

被引：24

作者：

Hauenschild, J ^{[1
]}

Dorschky, C ^{[1
]}

vonMohrenfels, TW ^{[1
]}

Seitz, R ^{[1
]}

机构：

[1] LUCENT TECHNOL,D-90411 NURNBERG,GERMANY

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 12期

关键词：

D O I：

10.1109/4.545832

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Architecture and realization of a 10 Gb/s clock and data recovering demultiplexer (CDR-DMUX) Lest chip fabricated ire a 0.7-mu m single poly, 16-GHz BiCMOS process are described, The first stage of the circuit is a combination of a 1:2 DMUX and a parallel early-late phase detector, both supplied with 5-GHz clocks from an external VCO. The plastic package does not measurably degrade the differential data input reflection. The 2.3 x 2.3 mm(2) chip dissipates 450 mW at -3.6 V.

引用

页码：2056 / 2059

页数：4

共 16 条

[1] CLOCK RECOVERY FROM RANDOM BINARY SIGNALS [J].