Thin L-shaped spacers for CMOS devices

被引：3

作者：

Augendre, E ^{[1
]}

Rooyackers, R ^{[1
]}

de ten Broeck, MD ^{[1
]}

Kunnen, E ^{[1
]}

Beckx, S ^{[1
]}

Mannaert, G ^{[1
]}

Vrancken, C ^{[1
]}

Vassilev, V ^{[1
]}

Chiarella, T ^{[1
]}

Jurczak, M ^{[1
]}

Debusschere, I ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256853

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents the use of ultimately thin (15 nm) L-shaped spacers to open the process window for deposition-related steps. Whereas conventional spacers prevent the correct active area silicidation between two closely located transistors, these thin L-shaped spacers allow the formation of a low resistive active interconnect between transistors as close as 40 nm apart. With respect to conventional spacers, thin L-shaped spacers show equally good silicide bridging immunity, device characteristics and electrostatic discharge performance.

引用

页码：219 / 222

页数：4

共 9 条

[1]

AUGENDRE E, 2001, 2 S USLI PROC INT EL, V2, P297

[2]

Chen M.-L., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P829, DOI 10.1109/IEDM.1990.237034

[3]

HENSON K, 2002, P ESSDERC, P563

[4] Significance of the failure criterion on transmission line pulse testing [J].