Embedded 5 V to 3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology

被引：59

作者：

den Besten, GW ^{[1
]}

Nauta, B ^{[1
]}

机构：

[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 07期

关键词：

CMOS integrated circuits; digital supply; fully integrated solution; low drop; power-down; replica control; series regulator; supply voltage compatibility;

D O I：

10.1109/4.701230

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated 5 V-to-3.3 V supply voltage regulator for application in digital IC's has been designed in a 3.3 V 0.5 mu m CMOS process. The regulator is able to deliver peak current transients of 300 mA, while the output voltage remains within a margin of 10% around the nominal value. The circuit draws a static quiescent current of 750 mu A during normal operation, and includes a power-down mode with only 10 mu A current consumption. The die area is 1 mm(2), and can be scaled proportional to the maximum peak current. Special precautions have been taken to allow 5 V in the 3.3 V process.

引用

页码：956 / 962

页数：7