An efficient strategy for developing a simulator for a novel concurrent multithreaded processor architecture

In developing a simulator for a new processor architecture, it often is not clear whether it is mora efficient to write a new simulator or to modify an existing simulator. Writing a new simulator forces the processor architect to develop or adapt all of the related software tools. However, modifying an existing simulator and related tools, which are usually not well-documented, can be time-consuming and error-prone. We describe the SImulator for Multitreaded Computer Architectures (SIMCA) that was developed with the primary goal of obtaining a functional simulator as quickly as possible to begin evaluating the superthreaded architecture [1, 2] The performance of the simulator itself was important, but secondary We achieved our goal using a technique called process-pipelining that exploits the unique features of this new architecture to hide the details of the underlying simulator: This approach allowed us to quickly produce a functional simulator whose performance is only 3.8 - 4.9 times slower than the base simulator.