Low-noise bias reliability of AlInAs/GaInAs MODFETs with linearly graded low-temperature buffer layers grown on GaAs substrates

被引：19

作者：

Wakita, AS ^{[1
]}

Rohdin, H ^{[1
]}

Robbins, VM ^{[1
]}

Moll, N ^{[1
]}

Su, CY ^{[1
]}

Nagy, A ^{[1
]}

Basile, DP ^{[1
]}

机构：

[1] Hewlett Packard Labs, Palo Alto, CA 94304 USA

来源：

1998 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS - CONFERENCE PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/ICIPRM.1998.712442

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

AlInAs/GaInAs MODFETs lattice-matched to InP have been shown to be reliable at low bias (V-ds = 0.75 to 1V) for low-noise applications [1-4]. Mean-times to failure (MTTF) from 10(5) to 10(7) hrs., based on various failure criteria, have been reported for lattice-matched FETs. To improve manufacturability of these FETs we have fabricated 0.1 mu m T-gate AlInAs/GaInAs MODFETs on mismatched GaAs substrates by the insertion of a compositionally linearly graded low-temperature buffer (LGLTB) layer [5]. In this work, we demonstrate that such FETs show comparable reliability at low-bias under high temperature operating life (HTOL) tests to FETs on InP. Although the LGLTB layer is highly defective, there is no indication that the low-bias reliability of these devices is compromised. Our AlInAs/GaInAs MODFETS, grown on GaAs, have an extrapolated MTTF, based on I-dss drift, exceeding 10(6) hours at a channel temperature of 125 degrees C.

引用

页码：223 / 226

页数：4