Integration of trench DRAM into a high-performance 0.18 μm logic technology with copper BEOL

被引：21

作者：

Crowder, S ^{[1
]}

Hannon, R ^{[1
]}

Ho, H ^{[1
]}

Sinitsky, D ^{[1
]}

Wu, S ^{[1
]}

Winstel, K ^{[1
]}

Khan, B ^{[1
]}

Stiffler, SR ^{[1
]}

Iyer, SS ^{[1
]}

机构：

[1] IBM Corp, Microelect Div, Hopewell Junction, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746527

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, we demonstrate the integration of trench DRAM into a 0.18 mu m copper BEOL technology which is fully compatible with our most advanced logic technology and requires no redesign of preexisting logic circuitry. This technology offers a 0.617 mu m(2) DRAM cell on the same chip as a 4.2 mu m(2) SRAM cell and dual damascene copper metallization with the highest reported device performance for a 1.5V bulk silicon technology. We demonstrate a fixable retention time of over 256 msec at 85 degrees C for the DRAM cell without any degradation in logic device performance or density.

引用

页码：1017 / 1020

页数：4