High performance metal gate MOSFETs fabricated by CMP for 0.1μm regime

被引：57

作者：

Yagishita, A ^{[1
]}

Saito, T ^{[1
]}

Nakajima, K ^{[1
]}

Inumiya, S ^{[1
]}

Akasaka, Y ^{[1
]}

Ozawa, Y ^{[1
]}

Minamihaba, G ^{[1
]}

Yano, H ^{[1
]}

Hieda, K ^{[1
]}

Suguro, K ^{[1
]}

Arikado, T ^{[1
]}

Okumura, A ^{[1
]}

机构：

[1] Toshiba Corp, Microelect Engn Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746473

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a plasma and thermal damage-free gate process named "Damascene gate process" where CMP (Chemical Mechanical Polishing) is used in forming gate structure. By using this process, fully planarized high performance metal (W/TiN or Al/TiN) gate transistors with pure SiO2 or Ta2O5 as gate insulators were fabricated with very uniform and highly reliable electrical characteristics. Therefore, this technology is useful in fabricating 0.1 mu m MOSFETs and beyond.

引用

页码：785 / 788

页数：4

共 4 条

[1] Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process
Chatterjee, A
Chapman, RA
Dixit, G
Kuehne, J
Hattangady, S
Yang, H
Brown, GA
Aggarwal, R
Erdogan, U
He, Q
Hanratty, M
Rogers, D
Murtaza, S
Fang, SJ
Kraft, R
Rotondaro, ALP
Hu, JC
Terry, M
Lee, W
Fernando, C
Konecni, A
Wells, G
Frystak, D
Bowen, C
Rodder, M
Chen, IC
[J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 821 - 824
[2] KAANTA W, 1991, P 8 INT VLSI MULT IN, P144
[3] LIN XW, 1998, SPRING M MAT RES SOC, P183
[4] SAITO T, 1998, SSDM, P154

← 1 →