A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression, A new family of highperformance parallel squarers based on the divide-and-conquer method is reported, Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six, This method reduced the gate count and provided shorter critical paths, A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-mu m CMOS fabrication technology, This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation.