Optimizing performances of switched current memory cells through a heuristic

Optimally designing switched current (SI) memory cells is a hard task. In addition, it is usually limited to the design of ideal cells. Thus, in this paper we deal with optimizing these cells and precisely real ones using a heuristic. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design this kind of cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias sources. The optimization procedure, developed with help of C++ software, allows automatic design of the cell. It is also highlighted in the followings.