Relation between trap creation and breakdown during tunnelling current stressing of sub 3 nm gate oxide

被引：15

作者：

Depas, M

Heyns, MM

机构：

[1] IMEC, B3001 Leuven

来源：

MICROELECTRONIC ENGINEERING | 1997年 / 36卷 / 1-4期

关键词：

D O I：

10.1016/S0167-9317(97)00008-7

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The wear-out of sub 3 nm gate oxide layers during tunnelling current stressing has been characterised by charge to breakdown (Q(BD)), tunnel current instability and stress induced leakage current (SILC) measurements. A correlation is found between the maximum value of the Q(BD) distribution and the amount of SILC for different tunnelling current stress conditions. The experimental results are consistent with the oxide breakdown model based on electron trap creation.

引用

页码：21 / 24

页数：4

共 10 条

[1]

DEGRAEVE R, 1995, TECHN DIG IEDM, P863

[2]

DEPAS M, 1996, EXT ABSTR SSDM, P533

[3]

DiMaria DJ, 1996, APPL PHYS LETT, V68, P3004, DOI 10.1063/1.116678

[4] HOLE TRAPPING, SUBSTRATE CURRENTS, AND BREAKDOWN IN THIN SILICON DIOXIDE FILMS [J].