Dual work function metal gate CMOS technology using metal interdiffusion

被引:146
作者
Polishchuk, I
Ranade, P [1 ]
King, TJ
Hu, CM
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
[2] Univ Calif Berkeley, Dept Mat Sci & Engn, Berkeley, CA 94720 USA
关键词
interdiffusion; metal gate CMOS; nickel; titanium; work function; x-ray photoelectron spectroscopy;
D O I
10.1109/55.944334
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this letter, we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve low threshold voltages for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not disturb the delicate thin gate dielectric and preserves its uniformity and integrity. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.
引用
收藏
页码:444 / 446
页数:3
相关论文
共 8 条
[1]   Gate length scaling and threshold voltage control of double-gate MOSFETs. [J].
Chang, L ;
Tang, S ;
King, TJ ;
Bokor, J ;
Hu, C .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :719-722
[2]   DIFFUSION IN TITANIUM AND TITANIUM-NIOBIUM ALLOYS [J].
GIBBS, GB ;
TOMLIN, DH ;
GRAHAM, D .
PHILOSOPHICAL MAGAZINE, 1963, 8 (92) :1269-+
[3]  
Lee CK, 2000, IEEE POWER ELECTRON, P27, DOI 10.1109/PESC.2000.878794
[4]   Ultra thin high quality Ta2O5 gate dielectric prepared by in-situ rapid thermal processing [J].
Luan, HF ;
Wu, BZ ;
Kang, LG ;
Kim, BY ;
Vrtis, R ;
Roberts, D ;
Kwong, DL .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :609-612
[5]  
NICOLLIAN EH, 1982, MOS PHYSICS TECHNOLO, P467
[6]  
SCHUEGRAF KF, 1993, P INT S VLSI TECHNOL, P86
[7]   High performance damascene metal gate MOSFET's for 0.1 μm regime [J].
Yagishita, A ;
Saito, T ;
Nakajima, K ;
Inumiya, S ;
Akasaka, Y ;
Ozawa, Y ;
Hieda, K ;
Tsunashima, Y ;
Suguro, K ;
Arikado, T ;
Okumura, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (05) :1028-1034
[8]   Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric [J].
Yeo, YC ;
Lu, Q ;
Ranade, P ;
Takeuchi, H ;
Yang, KJ ;
Polishchuk, I ;
King, TJ ;
Hu, C ;
Song, SC ;
Luan, HF ;
Kwong, DL .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (05) :227-229