Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

被引：12

作者：

Skotnicki, T ^{[1
]}

Jurczak, M ^{[1
]}

Martins, J ^{[1
]}

Paoli, M ^{[1
]}

Tormen, B ^{[1
]}

Pantel, R ^{[1
]}

Hernandez, C ^{[1
]}

Campidelli, I ^{[1
]}

Josse, E ^{[1
]}

Ricci, G ^{[1
]}

Galvier, J ^{[1
]}

机构：

[1] ST Microelect, F-38926 Crolles, France

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852807

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a new process of selective lateral under-etching of bi-layered Si/SiGe gates, aimed at formation of well-controlled notches. Weale Ga mole fraction (less than or equal to 30%) and moderate notch depth render the notch formation compatible with standard CMOS process, and prevent dispersions. The latter in the case of shallow notch (less than or equal to 25nm) are even smaller than in reference Si-gate devices without notch. Higher commutation speed, better transconductance and better SCE/DIBL immunity are demonstrated experimentally on notched gate devices.

引用

页码：156 / 157

页数：2

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