Error suppressing encode logic of FCDL in a 6-b flash A/D converter

被引：13

作者：

Ono, K ^{[1
]}

Matsuura, T ^{[1
]}

Imaizumi, E ^{[1
]}

Okazawa, H ^{[1
]}

Shimokawa, R ^{[1
]}

机构：

[1] HITACHI ULSI ENGN CORP,KODAIRA,TOKYO,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 09期

关键词：

A/D converter; encoder; folding; high-speed; logic; parallel;

D O I：

10.1109/4.628765

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 6-b, 166-Ms/s BICMOS Flash A/D converter was fabricated using a folded cascoded differential logic (FCDL), This FCDL reduces glitch errors caused by comparator metastability and improves encoder operation speed, The measured error rates of a chip implemented in a 0.7-mu m, f(t) = 12 GHz BiCMOS was less than 10(-10) times/sample. Without power-consuming highspeed track and hold circuit, the FCDL achieved low error rate and low power consumption of 505 mW at a 5.0-V power supply.

引用

页码：1460 / 1464

页数：5