A 0.135 μm2 6F2 trench-sidewall vertical device cell for 4Gb/16Gb DRAM

被引：8

作者：

Radens, CJ ^{[1
]}

Gruening, U ^{[1
]}

Mandelman, JA ^{[1
]}

Seitz, M ^{[1
]}

Dyer, T ^{[1
]}

Lea, D ^{[1
]}

Casarotto, D ^{[1
]}

Clevenger, L ^{[1
]}

Nesbit, L ^{[1
]}

Malik, R ^{[1
]}

Halle, S ^{[1
]}

Kudelka, S ^{[1
]}

Tews, H ^{[1
]}

Divakaruni, R ^{[1
]}

Sim, J ^{[1
]}

Strong, A ^{[1
]}

Tibbel, D ^{[1
]}

Arnold, N ^{[1
]}

Bukofsky, S ^{[1
]}

Preuninger, J ^{[1
]}

Kunkel, G ^{[1
]}

Bronner, G ^{[1
]}

机构：

[1] IBM Microelect, Semicond R&D Ctr, Hopewell Junction, NY 12533 USA

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852777

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 0.135 mu m(2) trench-capacitor DRAM cell with a trench-sidewall vertical-channel array device has been fabricated using 150 nm groundrules and optical lithography. This 6F(2) cell features a novel active area layout, a trench-top-oxide (TTO) isolation between trench capacitor and trench gate, maskless self-aligned buried strap node contact, shallow trench isolation (STI), a self-aligned poly-plug bit contact, and two levels of bitline interconnect, both formed using a W dual-damascene process.

引用

页码：80 / 81

页数：2

共 7 条

[1]

ALSMEIER J, 1997, S VLSI TECH, P19

[2]

Gruening U., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P25, DOI 10.1109/IEDM.1999.823838

[3]

HOENINGSCHMID H, 1998, S VLSI CIRC, P36

[4]

Radens C. J., 1998, S VLSI TECH, P36

[5]

Richardson W. F., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P714

[6]

RICHARDSON WF, 1989, VLSI S TECH, P65

[7]

Rupp T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P33, DOI 10.1109/IEDM.1999.823840

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