Thin-Layer Au-Sn Solder Bonding Process for Wafer-Level Packaging, Electrical Interconnections and MEMS Applications

被引：28

作者：

Belov, N. ^{[1
]}

Chou, T-K. ^{[2
]}

Heck, J. ^{[2
]}

Kornelsen, K. ^{[3
]}

Spicer, D. ^{[3
]}

Akhlaghi, S. ^{[3
]}

Wang, M. ^{[1
]}

Zhu, T. ^{[1
]}

机构：

[1] Nanochip Inc, 48041 Fremont Blvd, Fremont, CA 94538 USA

[2] Intel Corp, Santa Clara, CA 95054 USA

[3] Micralyne, Edmonton, AB T6N 1E6, Canada

来源：

PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2009年

关键词：

Wafer bonding; AuSn solder; electrical interconnects; bond gap control; sealing; thin bond line; low stress bonding; adhesion layer; solder wetting;

D O I：

10.1109/IITC.2009.5090361

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

080906 [电磁信息功能材料与结构]; 082806 [农业信息与电气工程];

摘要：

The developed bonding process utilizes AuSn solder and provides liquid-proof sealing and multiple reliable electrical connections between the bonded wafers. The bond can withstand 300 degrees C and features a thin bond line (2-3 mu m), high bond strength, excellent bond gap control, and low stress due to small amount of bonding material. A Nb/Au seed layer was shown to be an optimal adhesion and barrier film.

引用

页码：128 / +

页数：2

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