Silicon nanocrystal based memory devices for NVM and DRAM applications

被引：91

作者：

Rao, RA ^{[1
]}

Steimle, RF ^{[1
]}

Sadd, M ^{[1
]}

Swift, CT ^{[1
]}

Hradsky, B ^{[1
]}

Straub, S ^{[1
]}

Merchant, T ^{[1
]}

Stoker, M ^{[1
]}

Anderson, SGH ^{[1
]}

Rossow, M ^{[1
]}

Yater, J ^{[1
]}

Acred, B ^{[1
]}

Harber, K ^{[1
]}

Prinz, EJ ^{[1
]}

White, BE ^{[1
]}

Muralidhar, R ^{[1
]}

机构：

[1] Motorola Inc, SPS, Technol Solut Orga, Austin, TX 78721 USA

来源：

SOLID-STATE ELECTRONICS | 2004年 / 48卷 / 09期

关键词：

D O I：

10.1016/j.sse.2004.03.021

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Si nanocrystal based devices have shown potential in reducing the operating voltages used in continuous floating gate FLASH devices. We discuss the critical aspects of this technology-nanocrystal formation by CVD, nanocrystal passivation, and HCI/FN mode of operation of non-volatile memory bitcells fabricated using a 0.13 mum CMOS process technology. The superior FN erase characteristics of nanocrystal memory compared to a SONOS device are demonstrated, which enables the use of thicker tunnel oxides in nanocrystal memory devices as required to mitigate READ disturb. It is shown that nanocrystal area coverage of <25% is optimal for effective charge isolation and for 2-bit/cell applications. Finally the potential of this technology for use in a 1-transistor PMOS DRAM cell is discussed. (C) 2004 Elsevier Ltd. All rights reserved.

引用

页码：1463 / 1473

页数：11

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