Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology

被引：10

作者：

Arnal, V ^{[1
]}

Hoofman, RJOM ^{[1
]}

Assous, M ^{[1
]}

Bancken, PHL ^{[1
]}

Broekaart, M ^{[1
]}

Brun, P ^{[1
]}

Casanova, N ^{[1
]}

Chapelon, LL ^{[1
]}

Chevolleau, T ^{[1
]}

Cowache, C ^{[1
]}

Daamen, R ^{[1
]}

Farcy, A ^{[1
]}

Fayolle, M ^{[1
]}

Feldis, H ^{[1
]}

Furukawa, Y ^{[1
]}

Goldberg, C ^{[1
]}

Gosset, LG ^{[1
]}

Guedj, C ^{[1
]}

Haxaire, K ^{[1
]}

Hinsinger, O ^{[1
]}

Josse, E ^{[1
]}

Jullian, S ^{[1
]}

Louveau, O ^{[1
]}

Michelon, J ^{[1
]}

Posseme, N ^{[1
]}

Rivoire, M ^{[1
]}

Roman, A ^{[1
]}

Vandeweyer, T ^{[1
]}

Verheijden, GJAM ^{[1
]}

Torres, J ^{[1
]}

机构：

[1] STMicroelect, F-38926 Crolles, France

来源：

PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2004年

关键词：

D O I：

10.1109/IITC.2004.1345746

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Dual damascene integration of a porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k were investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.

引用

页码：202 / 204

页数：3